1. Field of the Invention
Generally, the present disclosure relates to the field of integrated circuits and, more particularly, to integrated circuits including nonvolatile memory devices.
2. Description of the Related Art
Nonvolatile memory, such as, for example, flash memory, may be used in various storage devices, such as, for example, secure digital memory cards (SD cards), USB sticks, solid state drives (SSDs), and internal memory of various electronic devices, such as, for example, mobile phones, tablet computers, media players, etc. Further applications of nonvolatile memory include embedded systems, wherein nonvolatile memory blocks including nonvolatile memory are provided in addition to logic devices and wherein the nonvolatile memory devices and the logic devices are physically and electrically integrated on a single substrate, for example, a single monolithic silicon substrate. Devices that may be provided on the monolithic silicon substrate in addition to nonvolatile memory cells may include field effect transistors and other circuit elements, such as capacitors, inductivities, diodes and/or resistors. Embedded systems including nonvolatile memory find applications in various fields, such as, for example, in automotive, industry and communication market segments. Integrating nonvolatile memory and logic circuitry on a single substrate may help to improve performance and reduce costs compared to solutions wherein nonvolatile memory and logic circuitry are provided on separate substrates, for example, due to an elimination of input/output buffers, design flexibility, lower power consumption and/or system-on-a-chip capability.
Types of nonvolatile memory cell architectures that have been used in embedded systems include one transistor cells (1T-cells) including a single gate, as well as split gate solutions such as 1.5 transistor (1.5T) and 2 transistor (2T) cells.
Examples of known nonvolatile memory cells include those described in U.S. Pat. Nos. 6,747,310 and 7,868,375. Nonvolatile memory cells as described in U.S. Pat. Nos. 6,747,310 and 7,868,375 include a source region and a drain region that are formed in a semiconductor substrate. Between the source region and the drain region, a channel region is provided that is doped differently than the source region and the drain region. Over the channel region, a floating gate and a select gate are provided. Over the floating gate, a control gate is provided, and an erase gate is provided over the source region. The select gate, the floating gate, the control gate and the erase gate are electrically insulated from each other and from the source, drain and channel regions by electrically insulating materials. The floating gate may be surrounded by electrically insulating material so that it is electrically floating. The source region, the drain region, the select gate, the control gate and the erase gate may have respective electrical contacts connected thereto so that voltages may be applied to the source region, the drain region and the select, control and erase gates for performing operations of programming, erasing and reading the nonvolatile memory cell.
For programming the nonvolatile memory cell, voltages adapted for creating a relatively strong, substantially vertically oriented electrical field in the channel region between the select gate and the floating gate may be applied to the select and control gates and the source and drain regions, which may cause a hot electron injection into the floating gate so that the floating gate is electrically charged. In particular, relatively high voltages of about 11 V may be applied to the control gate when the nonvolatile memory cell is programmed. Since the floating gate is electrically floating, the charge injected into the floating gate may remain in the floating gate and may create an electric field that acts on a portion of the channel region below the floating gate.
For reading data from the nonvolatile memory cell, a voltage may be applied between the source region and the drain region, and a voltage adapted for creating an electrically conductive channel below the select gate may be applied to the select gate. Due to the influence of the electric charge in the floating gate on the portion of the channel region below the floating gate, a current flowing between the source region and the drain region may be influenced by the electric charge of the floating gate. Thus, it can be determined if an electric charge has been injected into the floating gate by means of a programming operation.
For erasing the nonvolatile memory cell, a relatively high positive voltage of, for example, about 12 V may be applied to the erase gate. In doing so, a Fowler-Nordheim tunneling of electrons from the floating gate to the erase gate may be obtained. Thus, an electric charge injected into the floating gate in the programming of the nonvolatile memory cell may be removed from the floating gate. The select gate can provide a separation of the floating gate from the drain which may help to substantially avoid or at least reduce an overerase phenomenon.
In known nonvolatile memory cells, the select gate, the control gate, the erase gate and the floating gate may be formed of polysilicon, and silicon dioxide, silicon nitride and/or silicon oxynitride may be used for providing an electrical insulation between the select gate, the control gate, the erase gate and the floating gate and for providing an electrical insulation between the gates and the source, drain and channel regions of the nonvolatile memory cell.
Nonvolatile memory cells as described above have been implemented in the 40 nm technology node. However, implementing nonvolatile memory cells as described above in smaller technology nodes, for example in the 28 nm technology node, may have issues associated therewith. Relatively complex manufacturing processes may be required for forming known nonvolatile memory cells since a number of processes of deposition of polysilicon and chemical mechanical polishing may have to be performed for forming the select gate, the control gate, the erase gate and the floating gate, wherein manufacturing processes for forming the nonvolatile memory cells may have to be performed in addition to processes for the manufacturing of other devices such as transistors, resistors, capacitors, inductivities and/or diodes. In particular, there may be integration issues when transistors on the same substrate are formed in accordance with high-k metal gate (HKMG) technology. Moreover, there may be issues related to providing an appropriate electrical insulation between the gates of the nonvolatile memory cells while maintaining a good controllability of the channel region. Such issues may relate both to the electrical insulation between the control gate and the select and erase gates provided adjacent the control gate and to dielectric reliability properties of the insulation between the control gate and the floating gate provided below the control gate.
The present disclosure provides semiconductor structures including nonvolatile memory cells and methods for the formation thereof which may help to substantially overcome or at least reduce some or all of the above-mentioned issues.